1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof, and more specifically, to a capacitor and a method for forming the same.
2. Description of the Related Art
A variety of methods have been developed to implement simultaneously logic such as a CPU having a data processing function and memory having a data storage function. Furthermore, design techniques including analog, RF, etc., have been integrated into modern semiconductor manufacturing as well as logic and memory techniques.
Many elements including a transistor, a capacitor, and a resistor are integrated on a single chip in a semiconductor integrated circuit (IC). Efficient methods for implementing these elements have been diversely developed.
Capacitors, such as a PIP (Polysilicon/Insulator/Polysilicon) capacitor or a MIM (Metal/Insulator/Metal) capacitor, is often used in logic circuits such as CMOS logic. Such capacitors may be used in analog or digital circuits. Among these capacitors, a PIP capacitor is widely used for noise protection and frequency modulation. The bottom electrode and the top electrode of a PIP capacitor are manufactured using polysilicon. Polysilicon is also frequently used as a gate electrode material of a logic transistor so that the electrode of a PIP capacitor can be fabricated during the gate electrode's manufacturing.
FIG. 1 shows a semiconductor device having a PIP capacitor and a logic circuitry according to a conventional approach. As shown in FIG. 1, the device is divided into three parts i.e., a resistance region A, a capacitor region B, and a logic transistor region C.
A field area 3 determining an active area is defined in a substrate 1. A resistor 7 is formed in the resistance region A on the substrate. A PIP capacitor including a lower electrode 9, a dielectric layer 13, and an upper electrode 15 is formed in the region B. The MOS transistor including a gate electrode 11 and source/drain regions 10 is formed in the region C. The gate electrode 11 is formed on a gate insulating layer, while source/drain regions 10 are formed in the active area adjacent to the gate electrode.
A first ILD (Interlevel Dielectric) layer 17 and a second ILD layer 19 cover the top of the resistor, the PIP capacitor, and the transistor formed on the substrate. The contact plugs 21, 23, and 25 interconnect metal lines 27 and the elements on the substrate by penetrating these ILD layers 17 and 19. In a semiconductor device having the above-referred structure, the capacitance of a PIP capacitor is determined by the surface size of the dielectric layer disposed between a lower electrode and an upper electrode.
FIG. 2 shows a PIP capacitor according to a conventional art. Referring to FIG. 2, a PIP capacitor is formed from a lower electrode 9, a dielectric layer 13 and an upper electrode 15. The capacitance of the capacitor is determined by the surface size of the dielectric layer 13 between the upper electrode 9 and the lower electrode 15. A desired high capacitance can be obtained only by a relatively large line-width of polysilicon in the lower and the upper electrodes because the contact surface size of both electrodes determines the capacitance. For these reasons, currently, an analog device having a variety of characteristics in a substrate may have a lower cell density than other devices.